Overview
A functional 4-bit CPU designed from first principles in Logisim Evolution, featuring a custom instruction set, ALU, register file, and memory system.
This project demonstrates fundamental computer architecture concepts through hands-on implementation.
Architecture Components
Arithmetic Logic Unit (ALU)
- Addition and subtraction
- Bitwise AND, OR, XOR, NOT
- Comparison operations
- Carry/overflow flag generation
Register File
- 4 general-purpose registers (R0-R3)
- Dual-port read, single-port write
- Register-to-register operations
Control Unit
- Fetch-decode-execute cycle
- Instruction decoder with control signal generation
- Program counter with branch support
Memory System
- Separate instruction and data memory (Harvard architecture)
- 16-byte addressable data memory
- 256-byte instruction memory
Instruction Set Architecture
8 instructions implemented:
ADD,SUB- ArithmeticAND,OR,XOR- LogicalLOAD,STORE- Memory accessJMP,JZ- Control flow
Educational Value
Building a CPU from gates provides deep intuition for:
- How instructions execute at hardware level
- Pipeline and timing considerations
- Trade-offs in instruction set design
- The abstraction layers between software and silicon
Repository
The Logisim project file is available with documentation explaining each subsystem.